The present invention relates generally to analog-to-digital converters, more particularly, an efficient polyphase implementation of sigma delta analog-to-digital converter.
The advent of the Internet and the widespread popularity of personal computers have created an unprecedented demand for high bandwidth networks. Generally, Internet applications, from simple email to real time video conferencing, from web surfing to interactive movies, from interactive games to virtual TV stations, from online trading to online gambling, demand a higher bandwidth communication network. A fundamental challenge for the communication industry is to provide a reliable and affordable high bandwidth communication link to all types of Internet users. Various competing wire-line, wireless, and optical broadband technologies are deployed to partially meet the ever-increasing demand for higher bandwidth. The fastest growing broadband technology is the Digital Subscriber Line (DSL) technology, which provides a high bandwidth always-on connection over standard twisted pair copper media of the conventional telephone network. Among other wire-line media, coaxial cables are capable of providing always-on connections, however, its presence is insignificant compared to millions and millions of wired telephone customers who are connected by a twisted pair of copper wires. Other technologies, such as satellite, wireless, and optical, either provide limited coverage, limited bandwidth, or are too expensive for deployment to individual customers. As a result, DSL technology is uniquely positioned to provide the broadband link between individual customer premise and the central office, the so-called last-mile of the high-bandwidth communication network.
DSL is the fastest growing among emerging broadband technologies for very good reasons. First of all, DSL utilizes the existing copper wire network infrastructure. Secondly, compared to the voice modems, such as V.34 and V.90, used in most personal computers that provide up to 56 kbps dial-up connection, DSL provides a high bandwidth always-on connection with typical connection speeds from 384 kbps to 6 Mbps. Moreover, DSL is affordable with easy installation, simple turn-up, and high service reliability. The successful deployment of DSL is capable of providing digital broadband connection to anyone with an analog telephone line.
DSL services have been standardized over time by regional organizations such as, American National Standard Institute (ANSI), European Telecommunication Standard Institute (ETSI), and by world telecommunication organization International Telecommunication Union (ITU). These DSL standards define data communication protocols to connect customer premise equipment (CPE) to the central office (CO) and to provide connections to various networks, such as DSL service providers, virtual private networks (VPN), or the Internet. Various forms of digital data (e.g., voice, video, and data) can be transported using DSL technology. For transport of voice, DSL equipment is connected to the public switched telephone network (PSTN). For transport of video and data, DSL equipment uses the Internet via an Internet service provider (ISP). Voice over DSL (VoDSL) is capable of providing computer-to-computer, computer-to-telephone, and telephone-to-telephone voice services using an integrated access device (IAD). Video over DSL includes transport of MPEG-1 or MPEG-2 files, video conferencing using Internet Protocol (IP) standard such as ITU H.323, WebCam, and video mail. In addition, DSL supports simple data transport, e.g., bearer services, for virtual private network (VPN), leased data line such as T1 and E1, Point-to-Point Protocol (PPP), Asynchronous transfer mode (ATM), and Internet Protocol (IP).
Like other communication technologies, DSL has gone though a major evolution over the last decade and a collection of technologies, commonly referred to as xDSL, are developed under the umbrella of DSL. One type of subscriber loop digital transmission technology involves an integrated services digital network (ISDN), which has replaced a significant portion of the analog phone lines in Europe and Japan. ISDN offers integrated voice and data services and connection speed up to 144 kbps. Due to the high cost of deployment, an alternative solution called integrated digital loop carrier (IDLC) has been deployed in United States. However, resulting data rates were considered inadequate for individual customers. As a result, advanced DSL technologies were developed, which include HDSL, SDSL, ADSL, HDSL2, SHDSL, and VDSL, all of which are capable of connection speed in excess of 1 Mbps. These advanced DSL technologies were developed to address different needs and application demands, while serving different market segments. For example, SHDSL is a symmetric service designed for long reach office applications with connection speed of 1.5 Mbps, whereas, VDSL is designed to provide a very high-speed asymmetric service for a short-range applications.
SHDSL is a wire line Digital Subscriber Line (DSL) transmission technology that is designed to accommodate the need for higher data rates in telecommunication access networks. In particular, SHDSL supports duplex transmission of symmetric data rates over mixed gauge two-wire twisted metallic pairs, as described in the International Telecommunication Union (ITU) standard G.992.1xe2x80x94xe2x80x9cAsymmetric Digital Subscriber Line (ADSL) Transceiversxe2x80x9d, the body of which is incorporated herein by reference.
These and other drawbacks exist with current technologies.
Aspects of the present invention overcome the problems noted above, and realize additional advantages.
According to yet another aspect of an embodiment of the present invention, a polyphase combiner and sigma-delta decimator block structure is provided. An implementation of the structure is enabled by an effective decoupling of a polyphase Infinite Impulse Response (IIR) structure into a cascade of a polyphase Finite Impulse Response (FIR) bank and a single phase IIR filter. An embodiment of the present invention enables a reduction in hardware implementation by reducing timing requirements for filtering and power consumption through the use of a lower clock rate. An embodiment of the present invention provides a low complexity/low power consumption implementation of the combiner and decimator blocks through the use of a polyphase structure.
According to an embodiment of the present invention, an analog-to-digital converter comprises a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal; and a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.
In accordance with other aspects of this exemplary embodiment, the first combiner filter comprises a plurality of filters for receiving a plurality of input sequences and for generating a plurality of outputs; an adder for summing the plurality of outputs and for generating a first sum; and a first filter for receiving the first sum and for generating a first filtered output; the first filter comprises first filter coefficients defined       as    ⁢          xe2x80x83        ⁢          {                        f1          k                ;                  xe2x80x83                ⁢                  k          ⁢                      xe2x80x83                    ∈                      xe2x80x83                    ⁢                      {                          0              ,                              xe2x80x83                            ⁢              …              ⁢                              xe2x80x83                            ,                              xe2x80x83                            ⁢                                                L                  F1                                ⁢                                  xe2x80x83                                -                                  xe2x80x83                                ⁢                1                                      }                              }                  where      ⁢              xe2x80x83            ⁢              L        F1              =          {                                                                                                                              K                      ⁢                                              xe2x80x83                                            +                                              xe2x80x83                                            ⁢                      1                                        2                                                                                        when                    ⁢                                          xe2x80x83                                        ⁢                    K                    ⁢                                          xe2x80x83                                        ⁢                    is                    ⁢                                          xe2x80x83                                        ⁢                    odd                                                                                                                                          K                      2                                        ⁢                                          xe2x80x83                                        +                                          xe2x80x83                                        ⁢                    1                                                                                        when                    ⁢                                          xe2x80x83                                        ⁢                    K                    ⁢                                          xe2x80x83                                        ⁢                    is                    ⁢                                          xe2x80x83                                        ⁢                    even                                                                                                                          and                ⁢                                  xe2x80x83                                ⁢                                  f1                  k                                            =                              (                                                                            n                                                                                                                          2                        ⁢                                                  xe2x80x83                                                ⁢                        k                                                                                            )                                                        
where kxcex5{0, . . . , LF1xe2x88x921}; the input sequences comprises at least an even sub-sample and an odd sub-sample; the second combiner filter comprises a plurality of filters for receiving a plurality of input sequences and for generating a plurality of outputs; an adder for summing the plurality of outputs and for generating a second sum; and a second filter for receiving the second sum and for generating a second filtered output; the second filter comprises second filter coefficients defined as {f2k; kxcex5{0, . . . , LF2xe2x88x921}} where       L    F2    =      {                                                                                                                                  K                      ⁢                                              xe2x80x83                                            +                                              xe2x80x83                                            ⁢                      1                                        2                                                                                        when                    ⁢                                          xe2x80x83                                        ⁢                    K                    ⁢                                          xe2x80x83                                        ⁢                    is                    ⁢                                          xe2x80x83                                        ⁢                    odd                                                                                                                    K                    2                                                                                        when                    ⁢                                          xe2x80x83                                        ⁢                    K                    ⁢                                          xe2x80x83                                        ⁢                    is                    ⁢                                          xe2x80x83                                        ⁢                    even                                                                                                          xe2x80x83                                          ⁢              
            ⁢                                                                  and                ⁢                                  xe2x80x83                                ⁢                                  f2                  k                                            =                              (                                                                            n                                                                                                                                                    2                          ⁢                                                      xe2x80x83                                                    ⁢                          k                                                ⁢                                                  xe2x80x83                                                +                                                  xe2x80x83                                                ⁢                        1                                                                                            )                                                                        xe2x80x83                                                                          k                ⁢                                  xe2x80x83                                ∈                                  xe2x80x83                                ⁢                                  {                                      0                    ,                                          xe2x80x83                                        ⁢                    …                    ⁢                                          xe2x80x83                                        ,                                          xe2x80x83                                        ⁢                                                                  L                        F2                                            ⁢                                              xe2x80x83                                            -                                              xe2x80x83                                            ⁢                      1                                                        }                                            ;                                          
the input sequences comprises at least an even sub-sample and an odd sub-sample; a combiner adder for adding the first filtered output of the first filter and the second filtered output of the second filter; the first integrator filter comprises a Kth order integrator filter comprising a cascade of K integrators; the first downsampling block having a first subsampling factor; and the first differentiator comprises a Kth order differentiator comprising a cascade of K differentiators; where K is an integer greater than 1; and the second integrator filter comprises a Kth order integrator filter comprising a cascade of K integrators; the second downsampling block having a second subsampling factor; and the second differentiator comprises a Kth order differentiator comprising a cascade of K differentiators where K is an integer greater than 1.
According to another embodiment of the present invention, a method for implementing an analog-to-digital converter, comprises the steps of receiving a plurality of inputs by a first filter and a second filter; generating a combined signal in response to the plurality of inputs; receiving the combined signal; generating a digital sigma-delta output in response to the combined signal, wherein the digital sigma-delta output is generated by at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the description, serve to explain the principles of the invention.